1. Field of the Invention
The present invention relates to a semiconductor memory and, more particularly to a dynamic memory and also a dynamic memory system, capable of performing either RAS time-out function or a function equivalent thereto, in accordance with a RAS signal supplied from an external device.
2. Description of the Related Art
To use a conventional dynamic random-access memory (hereinafter referred to as "DRAM"), the user must input a RAS (Row-Address Strobe) to the memory at the timing shown in FIG. 11. Recently, a new type of a DRAM has been developed which has a RAS time-out function and can automatically maintain an internal row-address strobe (RINT) at an active level (i.e., a low level) for a prescribed period as is illustrated in FIG. 13, in response to the row-address strobe (RAS) supplied from an external device.
Due to the RAS time-out function, the user need not care about the timing of precharging the RAS to a high level, and it is easy for him or her to use the DRAM. Also, due to the RAS time-out function, the data stored in the memory cells of the DRAM remains undestroyed even if noise enters the RAS, inevitably precharging the RAS.
The RAS time-out function is indeed helpful in this respect, but it raises the following problems when it is applied to a high-integration, high-speed DRAM.
As is shown in FIG. 14, there are two terms during which signals can be input to a DRAM. The first is a RAS-active term tRAS, and the second is a RAS-precharge term tRP. The cycle time tRC of the DRAM is given as follows: EQU tRC=tRAS+tRP+2tT (1)
where tT is the transition time tT required for switching the RAS from the low level to the high level, or vice versa. The lower limits for tRC, tRAS, tRP, and tT are predetermined, as is shown in the following table. This means that the DRAM must be operable normally even if tRC, tRAS, tRP, and tT are reduced to these minimum values.
______________________________________ tRC min 150 ns tRAS min 80 ns tRP min 60 ns tT min 5 ns ______________________________________
One of the advantages of the RAS time-out function is that the lower limit is not set to tRAS. (If the lower limit is set, the RAS must be held at the low level for the period of 80 ns, as can be understood from the above table.) Hence, the user can set the RAS at the high level much earlier than the case where a lower limit is set to tRAS. Since the number of critical timings of operation the DRAM is thus reduced by one, it becomes easy for the user to use the DRAM. However, the DRAM must have a timer for maintaining the internal RAS (i.e., the RINT) for 80 ns.
In the conventional DRAM, which is not able to perform the RAS time-out function, the potential of a word line increases to supply data stored in a memory cell to a bit line, upon lapse of some time after the RAS has switched to the low level, as can be understood from FIG. 12. At the time a potential difference is made between the pair of bit lines, the sense amplifier connected between these bit lines is activated, thus amplifying the potential difference. When the RAS is switched to the high level, the potential of the word line decreases, whereby the data is stored into the memory cell. The moment the potential of the word line decreases to 0 V, these bit lines are equalized to potential VCC/2, where VCC is the power-source potential.
The higher the integration density and speed of the DRAM, the longer the sense amplifier requires to amplify the potential difference between the pair of bit lines, and at the same time, the shorter the time allowed for the restoring of the bit lines. For instance, if the RAS access time is 80 ns (as in a 4M-bis DRAM of the first generation), tRASmin is 80 ns, and the bit lines must be restored within 80 ns. Further, in the case of a 4M-bit DRAM manufactured by the conventional method and having three polysilicon layers and one aluminum layer, the bit line must be restored within only 20 ns after the P-channel sense amplifier has been activated, when VCC=4 V, Vtn=1.0 V, Vtp=-1.0 V, and Tc=85.degree. C.--all being the worst conditions possible. (Vth is the threshold voltage of the N-channel transistors used in the DRAM, and Vtp is that of the P-channel transistors used therein.) It is practically impossible to restore the bit lines to a sufficiently high level within so short a time as 20 ns.
The time required for sensing and amplifying the potential difference between the pair of bit lines can be reduced by using a multi-level metal wiring technique. The use of such technique requires a more complex method to manufacture the DRAM, and results in a higher cost of the DRAM. Hence, in the DRAM unable to perform RAS time-out function, if the RAS is precharged within the tRASmin, the potential of each word line inevitably will decrease to 0 V before the potential difference between the bit lines is sufficiently amplified. Consequently, sufficient data cannot be stored into the memory cell, inevitably causing soft errors and impairing the data holding characteristic of the DRAM.
To avoid soft errors and the deterioration of data holding characteristic, the DRAM must be modified to perform the RAS time-out function and be equipped with a timer to hold the internal RAS (i.e., RINT) at the low level for a period longer than tRASmin of 80 ns. If the DRAM is so modified and has a timer, the potential difference between the bit lines will be sufficiently amplified within the tRAMmin of 80 ns, provided that the potential of each word line reduces to 0 V and the pair of bit lines are equalized to potential VCC/2, fully within the tRPmin of 60 ns.
However, when the timer holds the internal RAS at the low level for a period longer than tRASmin of 80 ns, a problem will arise. If the data-reading operation is prohibited during the preceding operation cycle of the DRAM (for example RAS only refresh cycle), no data should be read from the DRAM during a period tRPC starting at the precharging of the RAS and ending at the activation of CAS (Column-Address Strobe) as shown in FIG. 4. (The period tRPC must have its minimum value of 0 ns even if tRASmin is 80 ns.) This condition cannot be satisfied when the internal RAS is set at the low level longer than tRASmin of 80 ns.
As has been described, the RAS time-out function makes it unnecessary for the user to care about the timing of precharging the RAS to a high level, and also prevents the data stored in the memory cells of the DRAM from being destroyed even if noise enters the RAS. Nonetheless, this RAS time-out function cannot apply to a DRAM which has a higher integration density and operates at a higher speed, and in which a longer time is required to amplify the potential difference between each pair of bit lines, and the tRASmin is shorter. In order to lengthen the term tRAS, without changing the term tRC, the term tRP can be reduced internally. If this method is used, however, the term tRPC will fail to have its minimum value.
This problem results from the fact that the prior-art DRAM capable of performing the RAS time-out function has only one timer, and the output of this timer, i.e., the internal tRAS, controls all other circuits of the DRAM when the external tRAS is too short.